1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically to a layout and a circuit construction of MOSFET memory cells suitable for use as a large capacity memory such as on-chip cache memory, for instance.
2. Description of the Prior Art
Recently, there are many cases where memory cells are assembled in a logic LSI. These memory cells are called on-chip memory. For instance, a recent microprocessor LSI is assembled with a large capacity chip memory referred to as cache memory, and the microprocessor LSI on which one-port memory as large as several hundred kilo-bits is mounted has been reported. For several years, a memory whose capacity as large as this can be realized by use of only a general purpose memory LSI. Recently, however, a large capacity on-chip memory can be realized owing to the advanced microminiaturization in silicon process technique.
In this case, however, the area of the cache memory occupies as large an area of several percentage of the whole chip area of the microprocessor. In addition, it has been known that the performance of the microprocessor can be increased with increasing capacity of the cache memory, there exists such a tendency in the microprocessor that a cache memory of large capacity is mounted on the chip in as wide an area as possible.
As described above, in order to obtain a high performance logic LSI, it is an important technique to realize a memory cell of the smallest possible area on the chip.
At present, a static memory cell as shown in FIG. 6 is used for almost all the cache memories. Here, the static memory is constructed by four NMOS transistors 1, 2, 3 and 4 and two PMOS transistors 5 and 6, this static memory cell is referred to as six-transistor static memory cell or a perfect CMOS cell.
In more detail, two gates of the two transistors 1 and 2 are connected to a word line 10, and two drains of the transistors 1 and 2 are connected to two bit lines 11 and 12, respectively. A source of the transistor 1 and two drains of the two transistors 3 and 5 are connected in common to two gates of the transistors 4 and 6. On the other hand, a source of the transistor 2 and two drains of the two transistors 4 and 6 are connected in common to two gates of the transistors 3 and 5. Further, two sources of the transistors 5 and 6 are connected to a high potential voltage supply line, and two sources of the transistors 3 and 4 are connected to a low potential voltage supply line (grounded line). Therefore, data can be held or stored by the crossing structure of the feedback lines of these four transistors 3, 4, 5 and 6.
FIG. 7 is a plan view showing a standard layout of the static memory cell constructed as shown in FIG. 6. In FIG. 7, a diffusion layer arranged on a semiconductor substrate forms the drains and the sources of the MOSFET transistors 1, 2, 3, 4, 5 and 6; a poly silicon layer forms the word line 10, the gates of the MOSFETs 1, 2, 3, 4, 5 and 6 and local wires; a first metal layer forms local wires; and a second metal layer forms the bit lines 11 and 12 and local wires; the third metal layer form the high potential supply line and the low potential supply line (ground line) and the word line 10, respectively.
FIG. 8 is a cross-sectional view showing the layout of the same circuit shown in FIG. 7. Since the structure shown in FIG. 8 is well known in the art, the detailed description thereof is omitted here. Contact C formed on the source and drain S/D of the n- or p-MOSFET is connected to the first metal layer FML; and this first metal layer FML is connected to the second metal layer SML through a through hole V1, as shown.
Here, since the six-transistor static memory cell can be manufactured in accordance with the standard process technique for the logic LSI having three metal layers and one poly silicon layer, there exists such an advantage that some special purpose process techniques required for only the memory cell is not needed.
Further, a four-transistor static memory cell having an area smaller than that of the six-transistor static memory cell is well known. FIG. 9 is a circuit diagram showing this four-transistor static memory composed of four NMOSFETs 1, 2, 3 and 4 and two high resistances 7 and 8.
In more detail, two gates of the two transistors 1 and 2 are connected to the word line 10, and two drains of the transistors 1 and 2 are connected to the two bit lines 11 and 12, respectively. The source of the transistor 1 and the drain of the transistor 3 are connected to the gate of the transistors 4 and the high resistance 7. On the other hand, the source of the transistor 2 and the drain of the transistor 4 are connected to the gate of the transistor 3 and the high resistance 8. Further, two high resistances 7 and 8 are connected to the high potential voltage supply line, and the two sources of the transistors 3 and 4 are connected to the low potential voltage supply line (grounded line). Therefore, data can be held or stored by the crossing structure of the feedback lines of these two transistors 3 and 4 and the two high resistances 7 and 8.
The cell as described above is sometime referred to as a high resistance cell, in addition to the four-transistor cell.
FIG. 10 is a plan view showing a standard layout of the static memory cell constructed as shown in FIG. 9, in which the same reference numerals have been retained for similar parts or elements having the same functions as with the case shown in FIG. 9.
In FIG. 10, a diffusion layer arranged on a semiconductor substrate forms the drains and the sources of the MOSFET transistors 1, 2, 3 and 4 and the local wires; a first poly silicon layer forms the word lines 10, the gates of the MOSFETs 1, 2, 3 and 4, and the local wires; a second poly silicon layer forms the high resistance 7 and the high potential supply line; a first metal layer forms the low potential supply line (ground line), the word line 10, and the local wires; and the second metal layer forms the bit lines 11 and 12 and the local wires, respectively.
In the manufacturing process of the above-mentioned cell, although adopted to manufacture the general purpose SRAM, the formation of the second poly silicon layer, the first buried contact and the second buried contact are not adopted to manufacture the logic LSI. In other words, in order to manufacture the above-mentioned four-transistor static memory cell as shown in FIG. 9, some special purpose process techniques are additionally required. However, this four-transistor cell has such an advantage that the size can be reduced down to about 1/3 of the area of the six-transistor cell.
On the other hand, from the standpoint of the reduction in the memory cell area, a memory cell composed of one transistor and one capacitance (used for the DRAM) is the minimum in size. FIG. 11 shows this minimum cell, which is composed of an NMOSFET 2 having the drain connected to the bit line 12 and a gate connected to the word line 10, and a capacitance 9 connected between the source of the transistor 2 and the low potential voltage supply line. In this DRAM, however, since the access time is relatively slow, this cell cannot be used as a cache memory, in general.
In contrast with this, FIG. 12 shows a dynamic memory cell usable as the cache memory. This cell is basically the same in structure as that shown in FIG. 9, when the two high resistances 7 and 8 are removed in FIG. 9.
In order to realize the DRAM structure as shown in FIG. 12, the wiring layers are arranged as follows:
The diffusion layer arranged on a semiconductor substrate forms the drains and the sources of the MOSFET transistors 1, 2, 3 and 4, and the local wires; the poly silicon layer forms the word line 10, the gates of the MOSFETs 1, 2, 3 and 4, and the local wires; the first metal layer forms the low potential supply line (ground line), the word line 10, and the local wires; and the second metal layer forms the bit lines 11 and 12 and the local wires, respectively.
When constructed as described above, since no load resistance exists, a charge at an internal node of the transistor charged to the high potential can be held by the parasitic capacitance existing at this node. Therefore, in the case of the DRAM in general, refresh operation for rewriting the internal data at each time interval is needed. However, the four-transistor dynamic memory cell shown in FIG. 12 is provided with such an advantage that the data can be written by simply selecting the word line 10, which is different from the DRAM shown in FIG. 11. In other words, in the case of the memory cell as shown in FIG. 11, since the cell data is destroyed whenever the word line 10 is selected, it is necessary to repeat the rewrite operation by activating each sense amplifier.
As described above, in the case of the four-transistor dynamic memory cell, since the rewriting operation by use of the sense amplifier is not needed, the refresh operation can be very simplified.
Therefore, when the four-transistor dynamic memory cell is adopted, instead of the four-transistor static memory cell as shown in FIG. 9, since the special purpose manufacturing process for forming the second poly silicon layer and the second buried contact are not needed, it is possible to reduce the manufacturing cost thereof.
In this case, however, a problem arises when the normal read/write operation and the refresh operation occur at the same time. Here, however, as far as the four-transistor dynamic memory cell is used only as the four-transistor static memory, this problem can be solved by handling this concurrence as a cache miss and by keeping the normal operation waited. In other words, since the refresh time is as short as 100 .mu.sec (which corresponds to a reduction in cache hit ratio of about 0.01%), the performance of the cache memory hardly deteriorates.
In summary, since the conventional semiconductor memory devices are constructed as described above, there exist the following problems:
In the case of the six-transistor static memory cell as shown in FIG. 6, since the memory size thereof is several times larger than that of the four-transistor static memory, when assembled with the logic LSI, there exists a problem in that the capacitance of the cache memory cannot be increased.
On the other hand, in the case of the four-transistor static memory as shown in FIG. 9, although the cell size can be reduced as that of the general purpose SRAM, since the special purpose manufacturing process for forming one additional wiring layer and two additional contact layers are further required, there exists a problem in that the manufacturing cost thereof inevitably increases markedly.
In contrast with this, in the case of the four-transistor dynamic memory cell as shown in FIG. 12, since the cell size is as small as that of the four-transistor static cell and further since the number of the special purpose manufacturing process can be reduced, this cell is suitable for assembling the cache memory with the logic without deteriorating the performance thereof. In this case, however, since the special purpose manufacturing process (the buried contact) is needed, it is impossible to perfectly reduce the manufacturing cost thereof. In addition, there exists another problem in that the buried contact is high in resistance so that the operation margin of the cell is reduced. In particular, when seen from the layout standpoint, in the feedback portion of the NMOS latch, one buried contact is formed at one node of the feedback loop but two buried contacts are formed on the other node of the feedback loop. Therefore, the electrical characteristics at the two internal nodes in the cell are not symmetrical with respect to each other, with the result it is impossible to disregard the deterioration of the cell characteristics. In the case of the general purpose SRAM, although this problem can be solved by strengthening the management of the buried contact process or by screening the contacts by performing a special test, in the case of the logic LSI of small quantity and diversified models, it is difficult to strengthen the process management and to perform the special test for the on-chip memory. In addition, since the poly silicon wire is used as the feedback wire and since the resistance of the poly silicon is not low in comparison with that of metal, there arises another problem in that the operation margin of the cell is lowered.